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[AKD4118A-A] [km100300] 2009/08 - 1 - general description AKD4118A-A is the evaluation boar d for ak4118a, 192khz digital audi o transceiver. this board has optical and bnc connector to interfac e with other digital audio equipment. ? ordering guide AKD4118A-A --- evaluation board for ak4118a (a cable for connecting with printe r port of ibm-at compatible pc and a control software are packed wi th this. the control software does not operate on windows nt.) function ? digital interface -s/pdif : 8 channel input (optical or bnc) 2 channel output (optical or bnc ) - serial audio data i/f : 1 input/output (for dir deta out put/dit data input. 10-pin port) -b,c,u,v bit : 1 input/output port (10-pin port) -serial control data i/f 1 input/output port (10-pin port) rx0 rx1 ak4118a b,c,u,v control 5v gnd opt rx7 tx0 ser ial da ta out (for dir) reg 3.3v tx1 opt figure 1. AKD4118A-A block diagram *circuit diagram and pcb layout are a ttached at the end of this manual. a k4118a evaluation board rev.0 AKD4118A-A
[AKD4118A-A] [km100300] 2009/08 - 2 - evaluation board manual ? operating sequence (1) set up the power supply lines. [+ 5v] (red) = 5v [gnd] (black) = 0v each supply line should be distributed from the power supply unit. (2) set up the evaluation mode and jumper pins. (refer to the following item.) (3) connect cables. (refer to the following item.) (4) power on. the ak4118a should be reset once bringing pdn(sw2) ?l? upon power-up. ? evaluation modes (1) evaluation for dir (default) s/pdif in (optical or bnc) ? ak4118a ? serial data out (10pin port) s/pdif optical, xlr or bnc connector port2 (10pin header) mclk bick lr ck sdto ak4118a (dir) AKD4118A-A dac mclk bi ck lrck sdto the dir generates mclk, bick, lrck and s data from the received data through optical connector(port1: torx176) or bnc connector. th e AKD4118A-A can be connected with the akm?s dac evaluation board via 10-line cable. a. set-up of bi-phase input rx0 and rx1-7 should not select bnc at the same time. a-1. rx0 connector jp2(rxp0) jp3(rxn0) optical (port1) opt bnc bnc (j2) bnc bnc table 1. set-up of rx0 a-2. rx1, 2, 3, 4, 5, 6, and 7 can be inputted from a bnc (j2) connector only. only rx1, rx2 and rx 3 can be used in parallel mode . the jumper which selects the rx channel should be short. input rx1 rx2 rx3 rx4 rx5 rx6 rx7 jp4 jp5 jp6 jp7 jp8 jp9 jp10 jp short short short rx4 rx5 rx6 rx7 table 2. set-up of rx1, 2, 3, 4, 5, 6 and 7
[AKD4118A-A] [km100300] 2009/08 - 3 - a-3. set-up of ak4118a input path it sets up by sw 1_1 and sw 1_5 in parallel mode. please set up ips2-0 bits in serial mode. - ips1 pin (sw1_5) ips0 pin (sw1_1) ips2 bit ips1 bit ips0 bit input data 0 0 0 rx0 default 0 0 1 rx1 0 1 0 rx2 0 1 1 rx3 1 0 0 rx4 1 0 1 rx5 1 1 0 rx6 1 1 1 rx7 (in parallel mode, ips2 is fixed to ?0?) table 3. recovery data select b. set-up of clock input and output the signal level outputted/inputted from port2 is 3.3v. port2 dir 5 6 1 10 gnd gnd gnd gnd gnd mclk bick lrck sdto daux figure 2. port2 pin layout b-1. mcko1/mcko2 the output of mcko1 pin or mcko2 pin can be selected by jp12. the output frequency of mcko1/mcko2 is selected by ocks 1-0. output signal jp12 mcko1 mcko1 default mcko2 mcko2 table 4. set-up of mcko1/mcko2 ocks1 pin (sw3_2) ocks0 pin (sw3_3) ocks1 bit ocks0 bit (x?tal) mcko1 mcko2 fs (max) 0 0 256fs 256fs 256fs 96 khz default 0 1 256fs 256fs 128fs 96 khz 1 0 512fs 512fs 256fs 48 khz 1 1 128fs 128fs 64fs 192 khz table 5. master clock frequency select
[AKD4118A-A] [km100300] 2009/08 - 4 - b-2. set-up of input/output of bick and lrck please select sw 3_7 (dir_i/o) accord ing to the setup of audio format of ak4118a (refer to table 7). audio format sw3_7 (dir_i/o) slave mode 0 default master mode 1 table 6. set-up of dir_i/o c. set-up of audio format it sets up by sw 1_2, sw 1_3 and sw1_4 in parallel mode. please set up dif2-0 bit in serial mode. dif2 pin (sw1_4) dif1 pin (sw1_3) dif0 pin (sw1_2) lrck bick mode dif2 bit dif1 bit dif0 bit daux sdto i/o i/o 0 0 0 0 24bit, left justified 16bit, right justified h/l o 64fs o 1 0 0 1 24bit, left justified 18bit, right justified h/l o 64fs o 2 0 1 0 24bit, left justified 20bit, right justified h/l o 64fs o 3 0 1 1 24bit, left justified 24bit, right justified h/l o 64fs o 4 1 0 0 24bit, left justified 24bit, left justified h/l o 64fs o 5 1 0 1 24bit, i 2 s 24bit, i 2 s l/h o 64fs o 6 1 1 0 24bit, left justified 24bit, left justified h/l i 64-128fs i default 7 1 1 1 24bit, i 2 s 24bit, i 2 s l/h i 64-128fs i table 7. audio format d. set-up of cm1 and cm0 the operation mode of pll is selected by cm1 and cm 0. in parallel mode, it can be selected by sw3_1 and jp18. in serial mode, it can be selected by cm1-0 bits. cm1 pin (sw3_1) cm0 pin (jp18) cm1 bit cm0 bit (unlock) pll x'tal clock source sdto source 0 0 (cm0) - on on(note) pll(rx) rx default 0 1 (cdto/cm0=h) - off on x'tal daux 0 on on pll(rx) rx 1 0 (cm0) 1 on on x'tal daux 1 1 (cdto/cm0=h) - on on x'tal daux on: oscillation (power-up), off: stop (power-down) note: when the x?tal is not used as clock comparison for fs detection (xtl0, 1= ?1,1?), the x?tal is off. table 8. clock operation mode select
[AKD4118A-A] [km100300] 2009/08 - 5 - (2) evaluation for dit serial data in(10pin port) ? ak4118a ? s/pdif out(optical or bnc) s/pdif optical, xlr or bnc connector port2 (10pin h eader) mc lk bick lrck daux ak4118a (dit) AKD4118A-A adc mclk bick lrck daux * * in put t o th e fift h pin. mclk, bick, lrck and daux are input the via 10pin header (port2: dir). a. set-up of a bi-phase output signal tx0 and tx1 should not select an optical connector or a bnc connector at the same time. a-1. the data outputted from tx1 can be selected by ops12-10 bit. connector jp19 (tx1) jp14 (tx1) optical (port4) opt bnc bnc (j4) bnc bnc table 9. set-up of tx1 a-2. as for tx0, only the loop back mode of rx corres ponds. this mode is fixed to rx0 in parallel mode. in serial mode, it can be selected by ops02-00 bits. connector jp13 (tx0) jp19 (txp1) jp14 (txn1) optical (port4) opt open bnc bnc (j4) bnc open bnc table 10. set-up of tx0 b. set-up of clock input and output the used signals are mclk, lrck, bick, and daux. the signal level outputted and inputted from port2 is 3.3v. port2 dir 5 6 1 10 gnd gnd gnd gnd gnd mclk bick lrck sdto daux figure 3. port2 pin layout clock port i/o mclk port2 out bick port2 in / out lrck port2 in / out daux port2 in table 11. clock input/output
[AKD4118A-A] [km100300] 2009/08 - 6 - b-1. mcko1/mcko2 the output of mcko1 pin or mcko2 pin can be selected by jp12. the output frequency of mcko1/mcko2 sets up by ocks 1-0. output signal jp12 mcko1 mcko1 default mcko2 mcko2 table 12. selection of mcko1/mcko2 ocks1 pin (sw3_2) ocks0 pin (sw3_3) ocks1 bit ocks0 bit (x?tal) mcko1 mcko2 fs (max) 0 0 256fs 256fs 256fs 96 khz default 0 1 256fs 256fs 128fs 96 khz 1 0 512fs 512fs 256fs 48 khz 1 1 128fs 128fs 64fs 192 khz table 13. master clock frequency select b-2. set-up of input/output of bick and lrck please set up sw 3_8 (dit_i/o) according to the setup of audio format of ak4118a (refer to table 20). jp16 and 17 should be fixed to the ?dc? side. audio format sw3_8 (dit_i/o) slave mode 0 default master mode 1 table 14. set-up of dit_i/o c. set-up of audio data format please refer to table 7. d. set-up of cm1 and cm0 cm1 pin (sw3_1) cm0 pin (jp18) cm1 bit cm0 bit (unlock) pll x'tal clock source sdto source 0 0 - on on(note) pll(rx) rx default 0 1 - off on x'tal daux 0 on on pll(rx) rx 1 0 1 on on x'tal daux 1 1 - on on x'tal daux on: oscillation (power-up), off: stop (power-down) note: when the x?tal is not used as clock comparison for fs detection (xtl0, 1= ?1,1?), the x?tal is off. table 15. clock operation mode select
[AKD4118A-A] [km100300] 2009/08 - 7 - ? b, c, u, v inputs and output b(block start), c(channel status), u(user data) and v(validity) are inputted/outputted via 10pin header (port3: bcuv). pin arrangement of port3 has become like figure 3. port3 bcuv 6 5 10 1 gnd gnd gnd gnd gnd b c u vout vin figure 4. port3 pin layout ? serial control the ak4118a can be controlled via the printer port (parallel port) of ibm-at compatible pc. connect port6 (up-i/f) with pc by 10-line flat cable packed with th e AKD4118A-A. take care of the direction of connector. there is a mark at pin#1. the pin layout of port6 is as figure 5. mode sw1_6 jp18 4 wire serial l cdto/cm0=?h? iic h sda and cm0=?l?(note) note: in iic mode, the chip address is fixed to ?01?. table 16. set-up of parallel mode and serial mode port6 up i/f 10 9 2 1 nc cdto cdti ccl k csn gnd gnd gnd gnd gnd figure 5. port6 pin layout this evaluation board encloses control software. a softwa re operation procedure is included in an evaluation board manual.
[AKD4118A-A] [km100300] 2009/08 - 8 - ? toggle switch set-up sw2 pdn reset switch for ak4118a. set to ?h? during normal operation. bring to ?l? once after the power is supplied. ? led indication le1 int0 bright when int0 pin goes to ?h?. le2 int1 bright when int1 pin goes to ?h?. ? dip switch (sw1) set-up: -off- means ?l? no. switch name function default 1 ips0 set-up of ips0 pin. (in parallel mode) off 2 dif0 set-up of dif0 pin. (in parallel mode) off 3 dif1 set-up of dif1 pin. (in parallel mode) on 4 dif2 set-up of dif2 pin. (in parallel mode) on 5 ips1/iic set-up of ips1 pin. (in parallel mode) set-up of iic pin. (in serial mode) ?l?: 4 wire serial, ?h?: iic off 6 p/sn set-up of p/sn pin. ?l?: serial mode, ?h?: parallel mode off 7 test don?t care off 8 acks don?t care off ? dip switch (sw3) set-up: -off- means ?l? no. switch name function default 1 cm1 set-up of cm1 pin. (in parallel mode) off 2 ocks1 set-up of ocks1 pin. (in parallel mode) off 3 ocks0 set-up of ocks0 pin. (in parallel mode) off 4 psel don?t care off 5 xtl0 off 6 xtl1 see table 17 off 7 dir_i/o set-up of the transmission direction of 74ac245 ?l?: when inputting from port2, ?h?: when outputting from port2 on 8 dit_i/o don?t care off ? set-up of xtl1 and xtl0 sw3_6 sw3_5 x?tal frequency xtl1 xtl0 x?tal 0 0 11.2896mhz default 0 1 12.288mhz 1 0 24.576mhz 1 1 (use channel status) table 17. set-up of xtl1 and xtl0
[AKD4118A-A] [km100300] 2009/08 - 9 - ? jumper set up. no. jumper name function 1 d3v/vd set-up of power supply source for 74ac245. d3v : d3v (default) vd : vd 2 rxp0 set-up of rxp0 input circuit. opt : optical (default) bnc : bnc 4,5,6 rx1-3 set-up of rx1-3 input circuit. 7,8,9,10 rx4-7 rx4-7 set-up depending serial/parallel mode rx4-7 : serial mode (default) dif2-0,ips0 : parallel mode 11,12 dir mclk , dit mclk mcko set-up for port5(dit) and port2(dir) mcko1 : mcko1 of ak4118a (default) mcko2 : mcko2 of ak4118a 13 tx0 set-up of tx0 output circuit. opt : optical bnc : bnc (default) 18 sda/cdto set-up of sda/cdto pin. 4 wire serial : cdto/cm0=?h?. (default) iic : sda 19 txp1 set-up of txp1 input circuit. opt : optical (default) bnc : bnc
[AKD4118A-A] [km100300] 2009/08 - 10 - control software manual ? set-up of evaluation board and control software 1. set up the AKD4118A-A according to previous term. 2. connect ibm-at compatible pc with AKD4118A-A by 10- line type flat cable (packed with AKD4118A-A). take care of the direction of 10pin header. (please install the driver in the cd-rom when this control software is used on windows 2000/xp. please refer ?installation manual of control software driver by akm device control software?. in case of windows95/98/me, this installation is not n eeded. this control software does not operate on windows nt.) 3. insert the cd-rom labeled ?AKD4118A-A evaluation kit? into the cd-rom drive. 4. access the cd-rom drive and double-click the icon of ?AKD4118A-A.exe? to set up the control program. 5. then please evaluate acco rding to the follows. ? operation flow keep the following flow. 1. set up the control program acco rding to explanation above. 2. click ?write default? button. 3. then set up the dialog and input data. ? explanation of each buttons 1. [port setup] : set up the printer port. 2. [write default] : initialize the register of ak4118a. 3. [all write] : write all registers that is currently displayed. 4. [read all] : all the registers of ak4118a are read. 5. [function1] : dialog to write data by keyboard operation. 6. [f3] : dialog of sequential writing. 7. [save] : save the current register setting. 8. [open] : write the saved values to all register. 9. [write] : dialog to write data by mouse operation. 10. [read] : th e data corresponding to each register is read.
[AKD4118A-A] [km100300] 2009/08 - 11 - ? explanation of each dialog 1. [function1 dialog] : dialog to write data by keyboard operation address box: input register address in 2 figures of hexadecimal. data box: input register data in 2 figures of hexadecimal. if you want to write the input data to ak4118a, click ?ok? button. if not, click ?cancel? button. 2. [write dialog] : dialog to write data by mouse operation there are dialogs corres ponding to each register. click the ?write? button corresponding to each register to set up the dialog. if you check the check box, data becomes ?h? or ?1?. if not, ?l? or ?0?. if you want to write the input data to ak4118a, click ?ok? button. if not, click ?cancel? button. ? indication of data input data is indicated on the register map. red letter indicates ?h? or ?1? and blue one indicates ?l? or ?0?. blank is the part that is not defined in the datasheet. ? attention on the operation if you set up function1 dialog, input data to all boxes. attention dialog is indicated if you input data or address that is not specified in the datasheet or you click ?ok? button before y ou input data. in that case set up the dialog and input data once more again. these operations does not need if you click ?cancel? button or check the check box.
[AKD4118A-A] [km100300] 2009/08 - 12 - revision history date (yy/mm/dd) manual revision board revision reason page contents 09/08/05 km100300 0 first edition - important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor aut horized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akm assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akm. as used here: note1) a critical component is one whose failure to func tion or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or syst em is one designed or intended for lif e support or maintenance of safety or for applications in medicine, aeros pace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products , who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above conten t and conditions, and the buyer or distributor agrees to assume any and all responsib ility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.
5 5 4 4 3 3 2 2 1 1 d d c c b b a a ips1/iic ips1/iic p/sn p/sn xtl0 xtl1 xtl0 xtl1 pdn pdn daux daux mcko2 mcko2 bick sdto lrck mcko1 mcko1 bick sdto lrck title size document number rev date: sheet of ak4118a 0 AKD4118A-A-48lqfp a3 13 tuesday, august 04, 2009 title size document number rev date: sheet of ak4118a 0 AKD4118A-A-48lqfp a3 13 tuesday, august 04, 2009 title size document number rev date: sheet of ak4118a 0 AKD4118A-A-48lqfp a3 13 tuesday, august 04, 2009 dif0/rx5 dif1/rx6 dif2/rx7 pdn vin daux mcko1 mcko2 bick sdto lrck int0 int1 cm0/cdto/cad1 cm1/cdti/sda ocks1/cclk/scl ocks0/csn/cad ips1/iic xtl1 xtl0 avdd p/sn rx0 rx1 rx2 rx3 ips0/rx4 bout cout uout vout tx0 tx1 ovdd u1 ak4118a u1 ak4118a ips0/rx4 1 nc 2 dif0/rx5 3 test2 4 dif1/rx6 5 vss1 6 dif2/rx7 7 ips1/iic 8 p/sn 9 xtl0 10 xtl1 11 tvdd 13 nc/gp1 14 tx0/gp2 15 tx1/gp3 16 bout/gp4 17 cout/gp5 18 uout/gp6 19 vout/gp7 20 dvdd 21 vss2 22 mcko1 23 bick 26 mcko2 27 daux 28 xto 29 xti 30 pdn 31 cm0/cdto/cad1 32 cm1/cdti/sda 33 ocks1/cclk/scl 34 ocks0/csn/cad0 35 int0 36 avdd 38 r 39 vcom 40 vss3 41 rx0 42 nc 43 rx1 44 test1 45 rx2 46 vss4 47 rx3 48 vin/gp0 12 lrck 24 sdto 25 int1 37 c22 5p c22 5p cn4 cn4 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 c23 5p c23 5p x1 11.2896mhz x1 11.2896mhz 1 2 + c26 10u + c26 10u 1 2 cn2 cn2 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 cn3 cn3 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 + c19 10u + c19 10u 1 2 c20 0.1u c20 0.1u cn1 cn1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + c27 10u + c27 10u 1 2 c24 0.1u c24 0.1u c25 0.1u c25 0.1u + c21 0.47u + c21 0.47u 1 2 r61 10k r61 10k
5 5 4 4 3 3 2 2 1 1 d d c c b b a a +5v vd dir_i/o d3v p/sn/ans dvdd avdd avdd vin daux2 dvdd acks tvdd/vdd avdd dvdd d3v vd ovdd vd d3v d3v test test acks d3v ips1/iic vd p/sn/ans emck2 daux2 d3v/vd avdd title size document number rev date: sheet of main1 0 AKD4118A-A a3 12 tuesday, august 04, 2009 title size document number rev date: sheet of main1 0 AKD4118A-A a3 12 tuesday, august 04, 2009 title size document number rev date: sheet of main1 0 AKD4118A-A a3 12 tuesday, august 04, 2009 rx5 rx6 rx7 dif0 dif1 dif2/xsel opt bnc rx4 ips0 xlr mcko2 mcko1 mclk lrck sdto bick gnd gnd gnd l h d3v vd for u6 for u1, u2, u5 for u3, u4 avdd p/sn/ans acks rxn0 rxp0 rx1 rx2 rx3 avdd ips0/rx4 dif0/rx5 test dif1/rx6 dvdd dif2/xsel/rx7 pdn vin daux mcko1 mcko2 ovdd bick sdto lrck mcko2 mcko1 gnd gnd acks test p/sn/ans dif2/xsel ips0 dif0 dif1 ips1/iic avdd daux sw1 sw1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 j2 rx0 j2 rx0 c5 0.1u c5 0.1u jp8 jp8 c13 0.1u c13 0.1u r4 short r4 short c16 0.1u c16 0.1u c2 0.1u c2 0.1u jp12 dir_mclk jp12 dir_mclk l1 10u l1 10u c6 0.1u c6 0.1u r8 short r8 short jp11 dit_mclk jp11 dit_mclk port1 torx176 port1 torx176 out 1 vcc 3 gnd 4 gnd 2 6 6 5 5 t2 lp2950a t2 lp2950a out 1 gnd 2 in 3 sw2 pdn sw2 pdn u1 74lvc157 u1 74lvc157 1y 4 2y 7 3y 9 4y 12 1a 2 1b 3 2a 5 2b 6 3a 11 3b 10 4a 14 4b 13 g 15 a/b 1 jp1 jp1 c7 0.1u c7 0.1u u3 74ac245 u3 74ac245 a0 2 a1 3 a2 4 a3 5 a4 6 a5 7 a6 8 a7 9 b0 18 b1 17 b2 16 b3 15 b4 14 b5 13 b6 12 b7 11 dir 1 oe 19 jp10 jp10 r3 short r3 short + c15 47u + c15 47u r22 100k r22 100k r23 100k r23 100k cn2 cn2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 jp5 jp5 100k 100k r18 100 r18 100 d1 1s1588 d1 1s1588 r21 100 r21 100 port2 dir port2 dir 1 2 3 4 5 6 7 8 9 10 c1 0.1u c1 0.1u + c14 47u + c14 47u r10 100 r10 100 jp2 jp2 1 3 5 2 4 6 t3 ta48m33f t3 ta48m33f in out gnd r14 100 r14 100 r9 10k r9 10k r15 100 r15 100 jp9 jp9 r6 short r6 short l2 10u l2 10u c4 0.1u c4 0.1u r20 100 r20 100 r13 100 r13 100 jp4 jp4 c3 0.1u c3 0.1u r5 75 r5 75 + c8 10u + c8 10u + c11 47u + c11 47u r17 100 r17 100 r19 100 r19 100 u2b 74hc14 u2b 74hc14 3 4 jp7 jp7 r11 100 r11 100 u2a 74hc14 u2a 74hc14 1 2 cn1 cn1 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 r16 100 r16 100 r12 100 r12 100 r1 470 r1 470 rp1 47k rp1 47k 1 2 3 4 5 6 7 8 9 r7 short r7 short jp6 jp6
5 5 4 4 3 3 2 2 1 1 d d c c b b a a vd d3v vd d3v p/sn/ans d3v vin dir_i/o dit_i/o d3v tvdd/vdd ovdd dvdd ips1/iic emck2 d3v/vd title size document number rev date: sheet of main2 0 AKD4118A-A a3 22 tuesday, august 04, 2009 title size document number rev date: sheet of main2 0 AKD4118A-A a3 22 tuesday, august 04, 2009 title size document number rev date: sheet of main2 0 AKD4118A-A a3 22 tuesday, august 04, 2009 cm1/cdti/sda vin u vout c b opt da02-f sda cdto/cm0=h cm0=l scl/cclk sda/cdti csn sda(ack)/cdto psel xtl1/trans dir_i/o dit_i/o xtl0/cks1 ocks0/fs0 cm1/fs1 ocks1/fs2 b c vout tvdd tx0 txp1 txn1 ovdd ebick emck elrck int0 int1 cm0/cdto/cad1 ocks1/cclk/scl ocks0/csn/cad0 dvdd ips1/iic psel xtl0 xtl1 u xlr bnc opt txp1 c17 0.1u c17 0.1u jp18 sda/cdto jp18 sda/cdto cn4 cn4 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 r28 100 r28 100 r55 470 r55 470 r37 150 r37 150 r59 100 r59 100 le2 int1 le2 int1 u2c 74hc14 u2c 74hc14 5 6 r25 100 r25 100 u5 74lvc157 u5 74lvc157 1y 4 2y 7 3y 9 4y 12 1a 2 1b 3 2a 5 2b 6 3a 11 3b 10 4a 14 4b 13 g 15 a/b 1 r51 10k r51 10k r54 10k r54 10k r53 100 r53 100 r45 1k r45 1k r50 100 r50 100 u2d 74hc14 u2d 74hc14 9 8 rp2 47k rp2 47k 1 2 3 4 5 6 7 8 9 r33 1k r33 1k port3 bcuv port3 bcuv 1 2 3 4 5 6 7 8 9 10 jp19 jp19 1 3 5 2 4 6 r26 100 r26 100 r60 100 r60 100 r36 240 r36 240 r56 51 r56 51 sw3 sw3 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 port4 totx176 port4 totx176 gnd 1 if 2 vcc 3 in 4 5 5 6 6 jp13 tx0 jp13 tx0 r32 47k r32 47k r58 10k r58 10k r30 47k r30 47k port6 up-i/f port6 up-i/f 10 8 6 4 2 1 3 5 7 9 r47 1k r47 1k cn3 cn3 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 r48 10k r48 10k r24 100 r24 100 j4 tx0 j4 tx0 r31 47k r31 47k r29 47k r29 47k u6a 74ls07 u6a 74ls07 1 2 t5 1:1 t5 1:1 r27 100 r27 100 r52 470 r52 470 le1 int0 le1 int0 r57 10k r57 10k r49 470 r49 470

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